A 2-stage-pipelined 16 port SRAM with 590Gbps random access bandwidth and large noise margin

抄録

A 90nm CMOS, 64Kbit, 1.16GHz, 16 port SRAM with multi-bank architecture realizing 590Gbps random access bandwidth, 41mW power dissipation at 1GHz and 0.91mm² (13.9µm²/bit) area consumption is reported. Compared to conventional 16 port SRAM data, area and power consumption are reduced by factors 16 and 5, respectively, while maximum clock frequency is about a factor 2 higher.