IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
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Two-parallel Reed-Solomon based FEC architecture for optical communications
Seungbeom LeeChang-Seok ChoiHanho Lee
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2008 Volume 5 Issue 10 Pages 374-380

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Abstract

This paper presents a high-speed Forward Error Correction (FEC) architecture based on two-parallel Reed-Solomon (RS) decoder for 10 and 40-Gb/s optical communication systems. A high-speed two-parallel RS(255, 239) decoder has been proposed and the derived structure can also be applied to implement the 10 and 40-Gb/s RS FEC architectures. The implementation results show that 16-Ch. RS FEC architecture can operate at a clock frequency of 160MHz and has a throughput of 41Gb/s for the Xilinx Virtex4 FPGA. Also, RS FEC operates at a clock frequency of 400MHz and has a throughput of 102Gb/s for 0.18-µm CMOS technology.

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© 2008 by The Institute of Electronics, Information and Communication Engineers
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