IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 5 , Issue 10
Showing 1-6 articles out of 6 articles from the selected issue
LETTER
  • Junichi Kani, Ryogo Kubo, Mitsumasa Okada, Yukihiro Fujimoto, Kiyomi K ...
    2008 Volume 5 Issue 10 Pages 361-365
    Published: 2008
    Released: May 25, 2008
    JOURNALS FREE ACCESS
    This paper proposes and demonstrates an optical network unit (ONU) that is adaptive in both point-to-point (P2P) and point-to-multipoint (P2MP) optical access networks (OANs) based on Gigabit Ethernet. Use of the proposed ONU makes it possible for network operators to reduce their operational expenditure (OPEX) by controlling/managing necessary inventories as well as handling troubles due to ONU mis-connection.
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  • Farhad Mehdipour, Hamid Noori, Hiroaki Honda, Koji Inoue, Kazuaki Mura ...
    2008 Volume 5 Issue 10 Pages 366-373
    Published: 2008
    Released: May 25, 2008
    JOURNALS FREE ACCESS
    Reconfiguration latency has a significant impact on the system performance in reconfigurable systems. A temporal partitioning approach is introduced for partitioning data flow graphs for a reconfigurable system comprising a partial programmable fine-grained hardware. Residing eligibility inspired from the Universal gravitation law is introduced to depict the eligibility of a node to stay in succeeding configurations (partitions) and to prohibit it from being swapped in/out. Partitioning based on residing eligibility causes fewer nodes with different functionalities to be assigned to subsequent partitions. Thus, reconfiguration overhead time and also unused hardware space decreases due to common parts in consecutive configurations.
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  • Seungbeom Lee, Chang-Seok Choi, Hanho Lee
    2008 Volume 5 Issue 10 Pages 374-380
    Published: 2008
    Released: May 25, 2008
    JOURNALS FREE ACCESS
    This paper presents a high-speed Forward Error Correction (FEC) architecture based on two-parallel Reed-Solomon (RS) decoder for 10 and 40-Gb/s optical communication systems. A high-speed two-parallel RS(255, 239) decoder has been proposed and the derived structure can also be applied to implement the 10 and 40-Gb/s RS FEC architectures. The implementation results show that 16-Ch. RS FEC architecture can operate at a clock frequency of 160MHz and has a throughput of 41Gb/s for the Xilinx Virtex4 FPGA. Also, RS FEC operates at a clock frequency of 400MHz and has a throughput of 102Gb/s for 0.18-µm CMOS technology.
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  • G. C. Chung, Mohamad Yusoff Alias, T. C. Chuah
    2008 Volume 5 Issue 10 Pages 381-387
    Published: 2008
    Released: May 25, 2008
    JOURNALS FREE ACCESS
    One of the major issues in ultra wideband (UWB) communications is the need to resolve multipaths and eliminate severe intersymbol interference (ISI). Although the conventional Rake can achieve multipath diversity for the desired signals, it does not mitigate ISI. We propose an adaptive Rake receiver by introducing the least bit error rate (LBER) criterion into the design of its finger coefficients. Results show that the proposed receiver achieves better performance than the conventional Rake receiver and the minimum mean square error (MMSE)-Rake receiver at high data rate.
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  • Junichi Akita
    2008 Volume 5 Issue 10 Pages 388-393
    Published: 2008
    Released: May 25, 2008
    JOURNALS FREE ACCESS
    The picture element (pixel) in conventional image sensors are placed in the form of a lattice for ease of implementation. Lattice placement of pixels intrinsically has directional singularity on the clarity of image representation, and the clarity is significantly dependent on the directions of the objects in the image. For example, horizontal lines are perfectly represented, while slanted lines have jagged edges.
     In this paper, we describe the CMOS image sensor with the pseudorandom pixel placement that solves the problem of the directional singularity on the clarity of image representation, as well as its evaluation in terms of the clarity of image representation for slant lines.
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