IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
Delay testing of PD-SOI circuits
Morteza DamavandpeymaRasoul YousefiBehjat Forouzandeh
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2008 Volume 5 Issue 12 Pages 437-441

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Abstract

Partially depleted silicon-on-insulator (PD-SOI) technology is an appropriate fabrication process for high-performance/low-power VLSI designs. SOI provides circuits with smaller delay and dynamic power consumption. However performance enhances come along with increase in complexity of performance measurement and delay testing. Whereas the SOI transistors are faster than the bulks, there exists variation in delay caused by threshold voltage shifts that must be considered during the manufacturing test. This paper presents new scan elements to overcome difficulty of delay testing in PD-SOI circuits that its silicon area is comparable to other solutions.

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© 2008 by The Institute of Electronics, Information and Communication Engineers
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