IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Novel bootstrapped CMOS differential logic family for ultra-low voltage SoCs
Byung-Hwa JungSung-Chan KangJae-Hyuk OhYoon-Suk ParkYong-Ki KimYong-Gu KangJong-Woo KimBai-Sun Kong
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2008 Volume 5 Issue 18 Pages 711-717


This paper describes novel bootstrapped CMOS logic family operating at ultra-low supply voltages. The proposed logic family provides better switching performance than conventional bootstrapped logic family by isolating the bootstrapping circuit from timing-critical signal paths. The logic family also minimizes area overhead due to the bootstrapping circuit by adapting a differential structure having a single bootstrap capacitor shared between complementary outputs. Multi-input XOR/XNOR gates and 64-bit adders were designed in 0.18um CMOS process as test vehicles for assessing the performance. Comparison results indicate that the power-delay product of the proposed logic family is improved by up to 67% compared to conventional differential logic circuits at the supply voltage ranging from 0.5V to 0.8V.

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© 2008 by The Institute of Electronics, Information and Communication Engineers
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