A single event transient generated from a high-energy particle is capable of corrupting the status of a digital system. Not only in aerospace engineering, but even in terrestrial application system reliability is expected to worsen due to radiation effects as semi-conductor technology advances. In this paper, we introduce an incremental gate-sizing method for minimizing soft errors in gate-level designs. The target designs have constraints for marginal circuit area and path delay. The proposed heuristic algorithm searches for each driving strength of logic gates using modified topological order. It gives a more effective solution in large marginal constraints than the existing greedy approach. In the experiments, we show the effectiveness of our algorithm using several benchmark circuits synthesized by a 130nm cell library.

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We propose a VLSI design of Multi-Format Decoder (MFD) to support multiple video codec standards such as MPEG-2, MPEG-4, H.264 and VC-1. A decoupled MFD architecture is introduced in order to easily add or remove the codecs. The decoupled architecture preserves the stability of the previously designed and verified codecs. It also reduces the gate count by sharing the large-size common resources. The design size is 2.4M gates and the operating clock frequency is 225MHz in the 65nm process.

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This paper describes novel bootstrapped CMOS logic family operating at ultra-low supply voltages. The proposed logic family provides better switching performance than conventional bootstrapped logic family by isolating the bootstrapping circuit from timing-critical signal paths. The logic family also minimizes area overhead due to the bootstrapping circuit by adapting a differential structure having a single bootstrap capacitor shared between complementary outputs. Multi-input XOR/XNOR gates and 64-bit adders were designed in 0.18um CMOS process as test vehicles for assessing the performance. Comparison results indicate that the power-delay product of the proposed logic family is improved by up to 67% compared to conventional differential logic circuits at the supply voltage ranging from 0.5V to 0.8V.

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We have developed a false face reduction algorithm dedicated for face detection in an unconstrained environment, based on the discriminative facial T-shape region constructed by human eyes, nose, and mouth. The algorithm started with a detected face, through lighting compensation, normalization, facial T-shape region extraction, and eigenface selection using genetic algorithms to classify face/false face robustly. Results of face detection with and without the proposed false face reducer show substantial improvements on precision rate at a little loss of recall rate.

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In recent years, a cryptographic construct, called fuzzy vault, has been proposed, which aims to secure critical data (e.g., secret encryption key) with the fingerprint data in a way that only the authorized user can access the secret by providing the valid fingerprint, and some implementation results have been reported. However, all the previous results adopted the brute-force search to reconstruct the polynomial or skipped the procedure for the polynomial reconstruction. In this paper, we propose a fast polynomial reconstruction algorithm for the fuzzy fingerprint vault which can improve the execution time of the brute-force search by a factor of 300∼1,500.

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A flip-chip bonding method has been developed for fabricating ultrafine-pitch pad-to-pad interconnects. The method utilizes the preferential growth of Ni-B bridge layers on resin walls in a microscale cavity structure fabricated in the underfill resin between copper pads facing each other under some conditions of electroless Ni-B plating. In this method, the interconnect can be fabricated without loading and/or heating. By controlling the growth of the bridge layer on the resin walls in the microscale cavity under optimized plating conditions, the feasibility of ultrafine-pitch flip-chip bonding with a 10-µm pad pitch is experimentally demonstrated at a temperature of 60°C.

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In this report, we propose a new MMSE channel estimation algorithm for OFDM systems. It is well-known that time domain maximum likelihood estimators (MSEs) show highly accurate impulse response estimation by using the time domain long preamble of the OFDM frame. On the other hand, the impulse response estimation based on the minimum mean square error (MMSE) criterion achieves superior channel estimation in low SNR conditions; however, it requires prior statistical information such as delay profiles of channels. In addition, the computational complexity becomes large because of the inverse matrix calculation. In order to overcome these issues, we propose to estimate the power delay profile of the channel by using the MLE, and to suppress the increase of the computational complexity for the matrix inverse calculation by applying the conjugate gradient method without degradation of the PER performance.

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Two novel 1-bit Full Adder cells based on Majority Function and the similarity between the minterms of the Cout and Sum functions, are proposed. The cells offer higher speed and less Power-Delay Product (PDP) than the conventional and current implementations of the 1-bit Full Adder cells especially in low voltages. All the input patterns are used for simulation to obtain the delay and the power consumption parameters. Simulations demonstrate improvement in terms of PDP and significant improvement in terms of speed.

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In this paper, we present a novel six-transistor (6T) single-ended static random access memory (SE-SRAM) cell for ultra-low-voltage applications. The proposed design has a strong 2.65X worst case read static noise margin (SNM) compared to a standard 6T SRAM. A strong write-ability of logic ‘one' is achieved, which is problematic in an SE-SRAM cell with a 36% improvement compared to standard 6T SRAMs. A 16 × 16 × 32 bit SRAM with proposed and standard 6T bitcells is simulated and evaluated for read SNM, write-ability and power. The dynamic and leakage power dissipation in the proposed 6T SRAM are reduced by 28% and 21%, respectively, as compared to standard 6T SRAM.

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This paper presents a hybrid of simulating annealing (SA) and an evolutionary algorithm (EA) to determine the input pair that cause the maximum number of switching gates in a combinational circuit. We found that this combination provides better results than those obtained when only using either SA or EA.

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In synchronous sequential circuit design, clock gating is recognized as a useful technique to reduce the power consumption. Conventionally, the clock gating is synthesized after high-level synthesis. In this paper, we point out that the module binding in high-level synthesis has a significant impact on the power consumption of gated clock tree. Based on that observation, we use an integer linear program (ILP) to formally formulate the problem. Our objective is to find a module binding solution so that the power consumption (of gated clock tree) can be minimized. It is noteworthy to mention that our work is the first attempt to synthesize the clock gating in the high-level synthesis stage. Benchmark data consistently show that our approach can greatly improve the existing design flow.

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A new versatile voltage-mode biquadratic with four inputs and four outputs using two differential difference current conveyors(DDCCs), two grounded capacitors, and two resistors is proposed. The proposed circuit can act as a multifunction voltage-mode filter with one or three inputs and four outputs and can simultaneous realization of voltage-mode notch, highpass, bandpass and lowpass filter signals from the four output terminals, respectively, without any component choice conditions. On the other hand, it also can act as a universal voltage-mode filter with three inputs and a single output and can realize five generic voltage-mode filter signals from the same configuration without any component matching conditions. H-Spice and MATLAB simulations results are provided to demonstrate the theoretical analysis.

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Quadrature amplitude modulation (QAM) is an excellent modulation format for realizing optical communication systems with a high spectral efficiency aiming at 10bit/s/Hz. We describe a three-channel frequency division multiplexed (FDM) and polarization-multiplexed 1 Gsymbol/s, 64 QAM coherent transmission over a 160km SMF with a 1.4GHz spacing. The total capacity for each channel reaches 36Gbit/s in an optical bandwidth of 4.2GHz, resulting in a spectral efficiency of 8.6bit/s/Hz.

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