IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
A single ended 6T SRAM cell design for ultra-low-voltage applications
Jawar SinghDhiraj K. PradhanSimon HollisSaraju P. Mohanty
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2008 Volume 5 Issue 18 Pages 750-755


In this paper, we present a novel six-transistor (6T) single-ended static random access memory (SE-SRAM) cell for ultra-low-voltage applications. The proposed design has a strong 2.65X worst case read static noise margin (SNM) compared to a standard 6T SRAM. A strong write-ability of logic ‘one' is achieved, which is problematic in an SE-SRAM cell with a 36% improvement compared to standard 6T SRAMs. A 16 × 16 × 32 bit SRAM with proposed and standard 6T bitcells is simulated and evaluated for read SNM, write-ability and power. The dynamic and leakage power dissipation in the proposed 6T SRAM are reduced by 28% and 21%, respectively, as compared to standard 6T SRAM.

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© 2008 by The Institute of Electronics, Information and Communication Engineers
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