Ant colony based efficient triplet calculation methodology for arithmetic built-in self test

抄録

A new methodology of searching for an effective triplet set for an arithmetic built-in self-test is proposed. The proposed methodology minimizes both the number of triplets and the total test length using an ant colony optimization heuristic that iteratively selects the best triplet according to the fault coverage of each solution. Experimental results on the ISCAS 85 and ISCAS 89 benchmark circuits resulted in a 66.6% average triplet size reduction and a 62.7% average test length reduction compared to previous methodologies.