抄録
A mobile sensor system for very low level biological signals such as neuron spikes is required to implement with a scaled CMOS technology. For a key circuit of these systems, a chopper amplifier (CA) which suppresses DC offset and 1/f noise of MOS devices is widely used. However, the conventional CA consumes large power because it requires a wide-band amplifier exceed a chopping frequency and a post Low Pass Filter (LPF) for eliminating modulation noise. In this paper, a new CA architecture for reducing power consumption is presented. In the architecture, the demodulator is placed at the input of 2nd stage amplifier and the 2nd stage has a narrow band determined with a 1st pole. Moreover the post LPF is not required. The proposed CA was designed and simulated with a 0.18µm CMOS process and a 1.2V supply. When the ratio of chopping frequency and signal band width is set to 100 (=10kHz/100Hz), the power consumption of the CA is reduced to 1/88 (=7µW/616µW) compared with the conventional CA.
