Abstract
This work presents a frequency multiplier architecture using 50% duty cycle corrector of which it can double input clock frequency in a wide-range operation. The said frequency multiplier is simulated using a 0.18µm CMOS process parameters and the results show that the output operational frequency attained a wide range from 10-MHz to 2-GHz. Moreover, the proposed design dissipates a power consumption of 1.4mW and a lock time of 1.2us at 2-GHz output signal.
