We present a simple architecture for Spiking Neural Networks self-configuration. It consists in the hardware implementation of a simple Genetic Algorithm that may be used to obtain optimum network configurations. The proposed solution is applied to estimate the processing efficiency of different networks. Based on the results we develop a new performance metric to calibrate the processing capacity of SNNs.
Although today's branch predictors show high accuracy, the branch misprediction penalty is getting larger due to aggressive speculation and deeper pipelining. In order to reduce the miss penalty, we propose a fast and low-cost branch recovery scheme using the incremental register renaming (IRR) and the bit-vector based rename map table (BVMT). The IRR enforces the destination register number of the instruction stream to appear in non-decreasing order. With this incremental property of the IRR, the BVMT recovery scheme completely eliminates the roll-back overhead on branch misprediction. Thus, the instruction fetcher does not stop and it fetches instructions from the correct path immediately after the misprediction detected. The goal of our scheme is to prevent a processor from flushing the pipeline, even under branch misprediction. Consequently, the BVMT instantly reconstructs the map table to any mispredicted branch and it outperforms the conventional approach by an average of 10.93%.
This paper presents an enhancement to the bootstrapped switching circuit by improving the input range limitation for applying direct input with no dc offset voltage. Application of a Darlington pair in the structure of the conventional bootstrap circuit allows for proper operation of circuits requiring low supply voltage and direct high input swing signal with no dc offset voltage. The proposed circuit is simulated using HSPICE and 0.18µm CMOS technology. Total Harmonic Distortion (THD) measurements results in SNR values which meet the necessary performance requirements for low-voltage application of switched capacitor circuits.
We propose a novel compensation method based on a dispersion relation equation for the constrained interpolation profile (CIP) method. In our method, two additional operations are performed after the CIP calculation. One is to calculate the numerical attenuation constant $\widetilde\alpha$ and the numerical phase constant $\widetilde\beta$ from the dispersion relation equation using Newton-Raphson method. The other is product and sum operations to compensate for amplitude and phase from the calculated $\widetilde\alpha$ and the $\widetilde\beta$. As described in this paper, both the amplitude and the phase error have been compensated using our method.
A novel low-kickback-noise Class-AB latched comparator utilizing unilateralization technique is presented for high-speed folding and interpolating analog-to-digital converter (ADC).The load transistors are independent with the clock signal. So the comparator can suppress the kickback noise significantly and work at low power supply. Dummy transistors and neutralization technique are also introduced to further reduce the noise. The comparator is simulated in 0.18-µm standard digital CMOS technology. A very low kickback noise voltage of 0.14mV is realized at the differential input voltage of 300mV.The power dissipation is about 202µW at 1.8V supply voltage, 250MHz clock frequency.
A contents correction signature hashing scheme for fast string matching algorithm in high performance network intrusion detection systems is proposed. The objective is to design a highly scalable pattern matching system suitable for wide spreading similar varieties of malicious behaviors in network. Simulation results show the proposed method maintains the hash table evenly compared with general hash table and shows high scalability as the increase of signatures and 130% of performance gain compared with SNORT.
The Radio Frequency IDentification (RFID) tags collision problem has been analyzed in this paper. A novel ultra high frequency (UHF) RFID system scheme, which is based on combination of Dynamic Framed Slotted Aloha (DFSA) and Code Division Multiple Access (CDMA) with Orthogonal Variable Spreading Factor (OVSF) code, was proposed. The proposed scheme has an ability to identify at most m (the length of OVSF code) tags simultaneously in one time slot. The theoretical analysis and computer simulation show that the proposed solution has significant improvement in expected system throughput when compared to classical simplex DFSA system scheme.
A new circuit topology of an offset compensated class-AB sample-and-hold (S/H) amplifier using two sampling capacitors is described. Conventional class-AB S/H amplifiers have high power efficiency, but suffer from offset deviations of the internal amplifier. The proposed class-AB S/H amplifier is free from the offset deviation of the internal amplifier, while achieving high power efficiency comparable to conventional class-AB S/H amplifiers. Simulation results show that systematic offset of the proposed S/H amplifier is comparable to that of an offset-compensated class-A S/H amplifier and has faster settling speed than that of the class-A type amplifier.
A mobile sensor system for very low level biological signals such as neuron spikes is required to implement with a scaled CMOS technology. For a key circuit of these systems, a chopper amplifier (CA) which suppresses DC offset and 1/f noise of MOS devices is widely used. However, the conventional CA consumes large power because it requires a wide-band amplifier exceed a chopping frequency and a post Low Pass Filter (LPF) for eliminating modulation noise. In this paper, a new CA architecture for reducing power consumption is presented. In the architecture, the demodulator is placed at the input of 2nd stage amplifier and the 2nd stage has a narrow band determined with a 1st pole. Moreover the post LPF is not required. The proposed CA was designed and simulated with a 0.18µm CMOS process and a 1.2V supply. When the ratio of chopping frequency and signal band width is set to 100 (=10kHz/100Hz), the power consumption of the CA is reduced to 1/88 (=7µW/616µW) compared with the conventional CA.
We report the experimental observation of the generation of short electrical pulses in a switch line, which is a transmission line periodically loaded with electronic switches. Pulse-width compression was experimentally demonstrated in the test switch line, using discrete Esaki diodes as the switches.
Multi-strip resonator BPF is fabricated in the LTCC configuration. The center frequency is 3.5GHz, fractional bandwidth is 0.1 and 3-stage Chebyshev type is designed. The relative permittivity of the ceramic is 18.3, resulting in the size as small as 2.3 × 1.6 × 0.73mm. The in-band loss is 3.5dB, which could be reduced in the stable mass production state. The spurious suppression of more than 30dB is attained up to the frequency higher than 10GHz.
We derive a novel time-domain asymptotic solution for a transient whispering-gallery (WG) mode radiation from the aperture plane of a cylindrical concave conducting boundary. The WG mode is excited by a Gaussian-type modulated pulse source. We show that the WG mode radiation field propagates with the phase velocity coincident with the speed of light and the newly derived group velocity. The validity of the time-domain asymptotic solution is confirmed by comparing with the reference solution calculated numerically. We show that the asymptotic solution proposed here is easy to understand the physical phenomena of the transient WG mode radiation field.
This work presents a frequency multiplier architecture using 50% duty cycle corrector of which it can double input clock frequency in a wide-range operation. The said frequency multiplier is simulated using a 0.18µm CMOS process parameters and the results show that the output operational frequency attained a wide range from 10-MHz to 2-GHz. Moreover, the proposed design dissipates a power consumption of 1.4mW and a lock time of 1.2us at 2-GHz output signal.