IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Onyx: A new heuristic bandwidth-constrained mapping of cores onto tile-based Network on Chip
Majid JanidarmianAhmad KhademzadehMisagh Tavanpour
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2009 Volume 6 Issue 1 Pages 1-7


Due to the ever-increasing complexity of System on Chip (SoC) design, and non-efficiency of electric bus to exchange data between IP cores in Giga scale, the Network on Chip (NoC) is presented with more flexible, scalable and reliable infra-structure. As mapping of IP cores on a given platform is one of three aspects of NoC design, with the focus on tile-based NoC architecture, we have introduced a heuristic method for mapping cores on mesh platform. Onyx1 algorithm is a method with less complexity, and it minimizes hop count between IP cores, leading to improving energy consumption and other performance parameters. We have used this method with two real applications, i.e. VOPD2, and MPEG-4 and compared it with some existing algorithms. The results show that our developed method is more efficient.

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© 2009 by The Institute of Electronics, Information and Communication Engineers
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