Due to the ever-increasing complexity of System on Chip (SoC) design, and non-efficiency of electric bus to exchange data between IP cores in Giga scale, the Network on Chip (NoC) is presented with more flexible, scalable and reliable infra-structure. As mapping of IP cores on a given platform is one of three aspects of NoC design, with the focus on tile-based NoC architecture, we have introduced a heuristic method for mapping cores on mesh platform. Onyx1 algorithm is a method with less complexity, and it minimizes hop count between IP cores, leading to improving energy consumption and other performance parameters. We have used this method with two real applications, i.e. VOPD2, and MPEG-4 and compared it with some existing algorithms. The results show that our developed method is more efficient.
Number representations play important roles in improving the speed of arithmetic operations. In order to perform parallel computing, it is needed to represent the operands with fully or hybrid redundant encodings. Besides, symmetric digit set is useful in many applications. Hybrid redundant number systems can display some symmetric digit sets for radix-r. In a lemma proposed in  it was shown that there is no symmetric digit set [-α, α] for radix-r hybrid redundant number system with α<r-2. However we show that the lemma can't produce all possible symmetric digit set associated with periodic hybrid redundant representations. In the paper we propose a new algorithm to determine all symmetric digit sets in hybrid redundant number system.
In this paper, a concurrent CMOS LNA for GPS application is presented, which supports L1 and L5 only modes as well as L1 and L5 simultaneous mode. To achieve concurrent operation, new cascode configuration employing a single common-source input stage and two common-gate output stages is proposed. And the band-pass matching technique using two capacitor banks is applied to achieve gain and output return loss tunability. It is implemented using 0.13µm CMOS technology. The LNA achieved low noise figures of 1.68 and 1.67dB with high gains of 15.7dB and 16.7dB at L1 and L5 band, respectively and showed more than 10dB input and output return losses. The LNA chip consumes low current of 4.5mA from 1.2V supply.
Subband adaptive filters are preferred in acoustic echo cancellation systems with long echo tail lengths due to speed of convergence and complexity savings. Recently, a new and novel subband affine projection (SAP) algorithm was reported based on the polyphase decomposition of the adaptive filter and noble identities. For good system performance it is important to have a good variable step size (VSS) algorithm as part of an adaptive filter. In this paper, based on the method of delay coefficients (DC), we propose1 a VSS algorithm for the SAP adaptive filter, which is called as delay coefficients based variable step size subband affine projection algorithm (DC-VSS-SAP). We examine in detail the similarities and differences between DC method for the subband and fullband scenarios. Further, we show how the method of DC can be used to detect changes in echo paths and speed up convergence of the adaptive filter.
The NoC paradigm is one, if not the only one, fit to enable the integration of an exceedingly large number of computational, logical and storage blocks in a single chip. This paper presents a novel technique called CGMAP, which finds a mapping of the vertices of a task graph to the tiles of a mesh based NoC architecture. The proposed algorithm is basically a genetic algorithm, which takes the advantages of the chaotic systems by using them instead of the random processes in the GA.Experimental results show that the proposed algorithm performs as well as the previously proposed mapping algorithms considering some performance indexes such as hop distance, energy consumption, and latency ratio.
A new and simple bit transition detection technique for non-return-to-zero (NRZ) signals is described. The bit transition detector uses MOSFET transistor's nonlinearity to extract return-to-zero (RZ) signals from NRZ signals. The resulting RZ signals can be used for injection-locking an oscillator, performing clock synchronization. A 10Gbps injection-locked clock and data recovery (CDR) circuit is successfully demonstrated with the bit transition detector in 0.18µ m CMOS technology.
We demonstrate for the first time a multi-wavelength laser based on a bismuth-based erbium-doped fiber (Bi-EDF) assisted by a four-wave mixing (FWM) process. Using a simple linear cavity resonator scheme containing a 49cm long highly nonlinear Bi-EDF, we obtained about 8 lines of optical comb with a line spacing of approximately 0.52nm at the maximum 1480nm pump power of 160mW.
Performance of multi-processor simulation is determined by how often simulators exchange events with one another and how accurately simulators model their behaviors. Previous techniques have limited their applicability or sacrificed accuracy for performance. In this paper, we notice that inaccuracy comes from events which arrive between event exchange boundaries. We propose cycle accurate transaction-driven simulation which maintains event exchange boundaries at bus transactions but compensates for accuracy. The proposed technique is implemented in CATS framework and our experiment with 64 processors achieves 1.2M processor cycles/s.
Simulation results are provided for the modified nanoscale Field Effect Diode (FED) used as a variable gain amplifier in automatic gain control systems. Field Effect Diode is similar to regular MOS transistors with the exception of using two gates over the channel region and oppositely doped source and drain. Its current-voltage characteristic results in large gain, low power dissipation and better frequency response compared with automatic gain control systems based on regular CMOS transistors. An added feature is the lack of short channel effects in Field Effect Diodes.