A New folding & interpolating ADC structure with reduced DNL/INL

Abstract

A new structure of Folding and Interpolating (F&I) ADC with reduced DNL/INL for low-resolution high-speed applications is presented, which resolves multiple-bits from linear region of each fold to decrease interpolating factor (F_I) to two. It is analytically shown that by reducing F_I to two, DNL/INL due to systematic mismatch of current-mode interpolators is decreased, and the inherent unsystematic DNL of F&I ADCs is almost eliminated. A 6-bit 960MS/sec ADC in 0.18um CMOS process with 1.8V supply voltage is designed based on this structure. Results show an SNDR of 31.5dB, power dissipation of 88mW, while DNL/INL is below 0.35/0.4LSB.