IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
Area-delay efficient parallel architecture for Fermat number transform
Shuguo LiJian Zhang
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2009 Volume 6 Issue 8 Pages 449-455

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Abstract

The parallel Fermat number transform (FNT) architecture is usually implemented with the code conversion (CC) and the butterfly operation (BO) in the diminished-1 number system. However, both the CC and the BO require too much area and delay due to modulo 2n+1 carry-propagation addition. In this paper, we propose a novel parallel FNT architecture with the root of unity 2 which is mainly composed of carry-save code conversion (CSCC) and carry-save butterfly operation (CSBO).The CSCC and the CSBO remove the carry-propagation addition by exploiting the property of carry-save adders. Thus the proposed FNT architecture requires less area and delay than the previous one. Synthesis results using 0.13-µm CMOS standard cells library demonstrate the superiority of the resulting architecture against the previously reported solution.

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© 2009 by The Institute of Electronics, Information and Communication Engineers
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