抄録
Instability of SRAM memory cells derived from aggressive technology scaling has become one of the most significant issues. Although lowering the supply voltage for a memory cell (VDDM) improves a write margin, which increases the access time. In this paper, we propose a memory cell employing a Look-ahead Active Body-biasing (LAB) scheme for SOI-SRAM with the dynamic VDDM control. Simulation results have shown that the proposed SRAM cell shortens the access time by 54% in the write mode, while expanding read and write margins and reducing effects of variations in the threshold voltage on them.
