抄録
Nowadays, with technology shrinking and the huge demand for supporting multiple applications has led designers to use multiple IP cores within a single chip. Therefore, the designers have proposed Networks-on-chip to overcome the problems of future complex systems. Mapping IPs directly affects NoC design parameters such as latency and power consumption. In this paper we present a power and performance aware mapping technique based on the combination of both the bandwidth-constrained and branch and bound concepts. Results have shown improvements of the latency and power consumption of our technique when compared to other popular NoC mappings.
