A 5.7GHz low noise figure ultra high gain CMOS LNA with inter stage technique

Abstract

A 5.7GHz low noise ultra high gain CMOS LNA with inter stage technique is presented in this paper. The noise and gain performance is improved using common-source transistor inter stage network. A bias resistor of large value is placed between source and the body node to prevent body effect and reduce noise. The simulated 0.18µm CMOS LNA achieves -14dB and -17.5dB input and output return loss respectively. Compared to previously published current-reused LNA, the proposed LNA has the smallest noise figure of 1.85dB, extremely high gain 32.5dB, and the highest Figure of Merit of 87.28.