IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
A10b, 20-MS/s, 2.6mW fully differential CBSC pipelined ADC in 0.18µm CMOS
Majid ZamaniShahin Jafarabadi-AshtianiMasoud DoustiMohammad Naser-Moghadasi
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2010 Volume 7 Issue 23 Pages 1694-1701


In this paper a new structure for comparator-based switched-capacitor circuits has been presented. In contrast with the conventional architecture the proposed algorithm utilizes an extra comparator to make a variable comparator threshold, in order to attenuating the overshoot at the end of the coarse phase. for better designing we introduced some practical issues on preset levels designing. After that this paper proposes a feed forward offset compensation which can avoid offset accumulation in proposed architectures. Finally we designed a 10b 20MS/s Fully Differential CBSC Pipelined ADC with proposed architecture in a 0.18-µm standard CMOS process. It achieves 74.4-dB spurious-free-dynamic range (SFDR) and 58.34-dB SNDR. In addition It consumes 2.6mW from a 1.8-V power supply at 40MS/s, which obtains a figure of merit of 210fJ/step.

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© 2010 by The Institute of Electronics, Information and Communication Engineers
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