IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
A memory-efficient heterogeneous parallel pattern matching scheme in deep packet inspection
HyunJin KimHyejeong HongDongmyoung BaekJin-Ho AhnSungho Kang
Author information
JOURNALS FREE ACCESS

2010 Volume 7 Issue 5 Pages 377-382

Details
Abstract

This paper presents for hardware-based parallel pattern matching scheme that adopts heterogeneous bit-split string matchers for deep packet inspection (DPI) devices. Considering the pattern lengths, a set of target patterns is partitioned into two subsets for short and long patterns. By adopting the appropriate bit-split string matcher types for the two subsets, the memory requirements can be optimized for the bit-split parallel pattern matching engine. Experimental results show that the total memory requirements decrease by 39.40% and 20.52%, in comparison with the existing bit-split pattern matching approaches.

Information related to the author
© 2010 by The Institute of Electronics, Information and Communication Engineers
Previous article
feedback
Top