This paper presents the development of a real-time brain computer interface (BCI) system based on the detection of steady-state visual evoked potential (SSVEP). The system includes a frequency-programmable visual stimulator, EEG-band amplifier and filter, 16-bit data acquisition card, and signal processing and classification algorithms. Three visual stimuli flickering at varying frequencies were shown to the subject, and the system is able to identify the desired target that the subject was focusing on. Experiments on ten healthy subjects using the designed system yielded an average detection accuracy of 86.15%.
This letter proposes a fast parallel architecture and redundancy reduction algorithm for H.264/AVC intra4x4 prediction to speed up intra frame coding. A significant reduction in execution time is achieved without losing video quality. Only 204 cycles are required to process a macroblock (MB). Compared with the dedicated intra prediction , processing speed is enhanced by 79%.
The color recognition and identification in operation time is a critical task in color-based computer vision applications. The main problem for recognizing the real color arises when the color characteristics are changed dynamically in the life time of a system. The outdoor color models which have been addressed by some researchers have serious practical limitations to employ in real applications. Moreover, due to high fluctuations in environment illumination, using conventional classifier for discriminating colors is a complicated task. In this paper, a just-in-time and model-free solution in order to discriminate outdoor colors on data driven modality is proposed. For this purpose, adaptive similarity-based classifier is utilized to track the color's data evolution during a day.
We present a method, implementable on a field programmable gate array (FPGA), which allows real-time correction of video image distorted by the projection on a warped screen. The method is based on projecting a reference image, consisted of a mesh of reference points, onto the screen. The projected image is then acquired using a digital camera and compared to the original one to determine the parameters of the corrective transformation. The transformation uses a backward mapping algorithm and an anti-aliasing filter. Experimental results demonstrate that the presented FPGA implementation can significantly reduce geometrical distortion.
This paper analysis the conventional Comparator-Based Switched-Capacitor (CBSC) structure and presents a modified structure that uses interposing middle-phase in charge-transfer mode to solve the tight trade-off between accuracy, speed, and input-swing at no extra power. To meet the accuracy, speed and input-swing requirements, appropriate values of design parameters are analytically discussed and a procedure for choosing optimum values for design is presented. Moreover, digital controller for current sources and comparator are given for the new structure. The effectiveness of the proposed structure is verified through simulation of a gain-stage using a 0.13-um CMOS-technology with 1V power-supply and comparing with conventional CBSC.
Broadband optical switches are required for a wavelength division multiplexed photonic network node. The wavelength dependency of the LiNbO3 optical switch characteristics are mainly attributed to the directional coupler section. An asymmetric X-junction was suitable for a broadband optical switch because it has flat spectral response over wide wavelength range and it is easy to fabricate. We have optimized the structure of an asymmetric X-junction and fabricated the 1×2 LiNbO3 optical switches using it. The optical switch showed broad band characteristics compared to the switch with a directional coupler.
A new transmission protocol using MIMO (Multiple Input Multiple Output) half-duplex relays is proposed to improve the capacity and the diversity gain of uplink relay communication systems. The proposed protocol employs two half-duplex DF (Decode-and-Forward)relays and Alamouti coded 2×2 MIMO communication for links between each relay and the destination. A low complexity receiver using maximum ratio combining and Alamouti decoding is introduced to detect the signal of the proposed protocol. Performance is evaluated by theoretical analysis and computer simulations, and the results show that the proposed protocol outperforms conventional IEEE 802.16j systems in terms of ergodic capacity and outage probability.
The Automatic Gain Control (AGC) systems based on nanoscale Field Effect Diode (FED) and double gate silicon on insulator (SOI) MOSFET are investigated in this paper. Using double gate devices leads to more flexibility in gain controlling, improving performance, and power consumption reduction. Simulation results show these systems have better characteristics in terms of power and bandwidth in comparison with AGC system based on regular MOSFET. Among proposed alternative structures (SOI-MOS, MOSFET, FED), nanoscale FED is specifically suited for variable gain amplifier circuits in AGC systems which leads to improve performance and reduce power consumption in low-power applications.
This paper presents for hardware-based parallel pattern matching scheme that adopts heterogeneous bit-split string matchers for deep packet inspection (DPI) devices. Considering the pattern lengths, a set of target patterns is partitioned into two subsets for short and long patterns. By adopting the appropriate bit-split string matcher types for the two subsets, the memory requirements can be optimized for the bit-split parallel pattern matching engine. Experimental results show that the total memory requirements decrease by 39.40% and 20.52%, in comparison with the existing bit-split pattern matching approaches.