抄録
This paper propose an area-efficient pipeline-balancing Reed-Solomon decoder for 10Gbps satellite communication. The proposed RS (244,212) is based on TD-iBM Key Equation Solver architecture, and Fixed-Factor Syndrome Computation & Chien Search. The decoder is implemented and verified in FPGA, and can work at 178MHz in Virtex2P. Thus a 8-channel FPGA implementation can be used for 10Gbps satellite communication systems. Additionally, the decoder is also synthesized in Chartered 90nm CMOS technology, and compared with previous decoders. The results show the decoder is more area-efficient than previous decoders. Meanwhile, by using this CMOS technology, the decoder can be clocked at about 1350MHz, so a single-channel ASIC implementation can meet the requirement of 10Gbps satellite communication.
