抄録
The current paper presents thermalcode addition technology as applied to an LDPC decoder to replace a variable node unit in the traditional adder. The proposed irregular quantization of thermalcode addition can generate information with regularity, which makes addition to the variable node executable by combinational logic circuit. With the original BER performance, code rate 1/2, and matrix (1296,648) in 802.11n standard, the simulation and logic synthesis results reveal that the presented LDPC decoder can save up to 21% of the hardware area.
