2011 Volume 8 Issue 24 Pages 2041-2047
This paper presents a novel technique to shape feedback DAC mismatch without any extra digital elements inside the sigma-delta loop by inserting an analog integrator and an out-of-loop digital differentiator. To lower power dissipation, a novel triple integrator with low capacitor mismatch sensitivity of the delay paths is proposed. As a result, the SDM with three integrators is realized by only one OTA. The proposed topology, simulated at transistor level on 0.13µm CMOS process, achieves 98.4dB SNDR with 100kHz bandwidth and 1.2mW power dissipation from a single 1.2V supply voltage. Its specification satisfies the GSM requirements.