A novel large input range source-follower based filter architecture is proposed offering a increased 1-dB compression point, without increased power consumption. An alternative feedback mechanism enables single-ended use and simplifies the bias scheme. Simulation has confirmed a 250MHz second order filter stage consuming 40uA @ 1.2V supply in a 0.13um CMOS technology with 1-dB compression point at a differential peak to peak input amplitude of 1.4V, more than doubling the input range of previous implementations with similar power dissipation.
In this paper, a novel design approach for significant size reduction of a class of dual-band branch-line coupler (BLC) by use of a transmission line model loaded with a folded-T-type stepped-impedance-stub (FTTSIS) is proposed. At the first step, by loading FTTSIS at the middle of each branch instead of stepped-impedance-stub (SIS) in the conventional branch-line coupler, a compact dual-band BLC with same performance that is about 65% of the conventional one is achieved. Then by mirroring the FTTSISs of 35Ω lines inside the inner space of the proposed structure, miniaturized dual-band BLC that is only 30% of the conventional dual-band BLC operating at same WLAN frequencies is obtained. The proposed structure is then fabricated and measured. The measurement results show good agreement with the theoretical ones.
Accurate analytical modeling of IEEE 802.11 distributed coordination function (DCF) is very important to characterize IEEE 802.11 medium access control (MAC) layer performance. The two backoff procedures used in the IEEE 802.11 DCF, namely pre-backoff and post-backoff procedures, are commonly treated as the same in existing analytical DCF models for simplicity. This paper makes the first effort to point out the difference between these two backoff procedures. Through intuitive reasoning and simulation results, we show that the two backoff procedures yield un-negligible differences in the performance of average access delay, but give the same performance of throughput.
This paper presents a novel technique to shape feedback DAC mismatch without any extra digital elements inside the sigma-delta loop by inserting an analog integrator and an out-of-loop digital differentiator. To lower power dissipation, a novel triple integrator with low capacitor mismatch sensitivity of the delay paths is proposed. As a result, the SDM with three integrators is realized by only one OTA. The proposed topology, simulated at transistor level on 0.13µm CMOS process, achieves 98.4dB SNDR with 100kHz bandwidth and 1.2mW power dissipation from a single 1.2V supply voltage. Its specification satisfies the GSM requirements.
In this paper we re-call a recently developed meta heuristic optimization algorithm based on socio-political process of imperialistic competition. This Colonial Competitive Algorithm (CCA) has shown its efficient capability in comparison to convenient optimization algorithms like GA, PSO. In this study we investigate the synthesis problem of unequally linear space antenna using CCA and show the efficient convergence to obtain a pattern with acceptable Side Lobe Level.
We propose a novel method to compensate for the phase errors of a multilayered arrayed waveguide grating (AWG) used in a liquid-crystal-on-silicon (LCOS)-based wavelength selective switch (WSS). In this scheme, an additional LCOS is employed to externally compensate for the phase errors of the AWG in a layer-by-layer manner for both planes of polarization. This compensation scheme enables us to improve the yield of the WSS: specifically, we demonstrate that the additional LCOS drastically reduces the loss and polarization-dependent loss (PDL) of the WSS.
VLSI physical design algorithms are generally nonpolynomial algorithms with very long runtime. In this paper, we parallelize the Pathfinder global routing algorithm -a widely used FPGA routing algorithm- for running on multi-core systems to improve runtime of routing process. Our experimental results show that the runtime of proposed multi-threaded global routing reduces by 47.8% and 70.9% (on average) with 2 and 4 concurrent threads, respectively on a quad-core processor without any quality degradation.
In this paper, we demonstrate for the first time ring laser oscillation using a set of silicon (111) mirrors fabricated by microelectromechanical systems (MEMS) technology with a semiconductor optical amplifier (SOA) as an optical amplifier medium. Four (111) mirrors were fabricated perpendicular to a (110) silicon wafer surface to form an optical loop. The (111) mirrors were fabricated by a combination of deep reactive-ion etching (DRIE) and anisotropic wet etching, followed by electroplating with a highly reflective Au film. Adjusting the mirror alignment for the oscillation was not required because the mirrors were already precisely positioned with the accuracy of the crystal orientation. In experiments, oscillation began at an injection current of more than 110 mA into the SOA. We confirmed that both forward and backward propagating lasers oscillated simultaneously in a single mode. Our results will especially be useful for realization of next-generation optical MEMS ring laser gyroscopes.
A novel SNR estimator is presented for efficient estimation of SNR in wireless OFDM systems. Unlike the conventional SNR estimators, the proposed estimator calculates an SNR estimate in the time domain, which alleviates the usage of FFT. In addition, the SNR estimator effectively exploits a periodic feature of the OFDM preamble for accurate SNR estimation. Furthermore, the SNR estimator shows robustness to timing-offset. The simulation results indicate that the presented estimator is superior to the conventional SNR estimators in terms of NMSE in the case of imperfect synchronization under high frequency-selectivity channel.
A new technique with two different structures for linearization of active mixers in zero-IF receivers is presented. The proposed technique improves the IIP2 more than 20dB by removing the transconductance common mode current at the mixer's output and IIP3 more than 5dB in comparison with a basic Gilbert-cell mixer at equal conversion gain. Also, this technique allows us to use a single-ended input in a fully differential structure without needing a bulky and noisy balun. These improvements are achieved at the cost of 0.8dB increase in NF and also 0.6 mA more current dissipation in one structure.
A tunable optical dispersion compensator (TODC) that uses a high-resolution arrayed-waveguide grating and integrated resin lenses is reported. The dispersion tuning range is 1426ps/nm, three times larger than that in our previous report for the same type of TODC. A transmission experiment using a 43-Gbps carrier-suppressed return-to-zero differential quadrature phase shift keying (CSRZ-DQPSK) signal is also reported.
A new design of a color sensor circuit that can differentiate four colors and produce digital outputs is presented in this paper. The proposed circuit uses a photodiode as a light transducer and few additional electronic components. The advantage of the proposed architecture is that the number of required components is fixed regardless of the number of detected colors with only increasing the number of component inputs. This feature is important especially in element count and low power consumption. The sensor circuit is implemented on a breadboard with commercially available off-the-shelf electronic components. The objective of this work is to validate a new architecture of color sensor circuit design using simulation and experimental analysis as a proof of concept for a future implementation as integrated circuit.
A wavefront matching design method is successfully applied to a high-index-contrast InP waveguide for the first time. Fabricated 2×2MMI coupler exhibits a 1.6 times wider operation wavelength range than a conventional MMI coupler. This coupler has less waveguide-width sensitivity and is suitable for InP-based large-scale photonic integrated circuits.
The power consumption of the 2D memory restricts its usage in vector DSPs for sliding-window applications with irregular memory accesses. This paper introduces a novel Low-Power 2D memory (LP2D), which can effectively reduce the power consumption to the traditional 2D memory without sacrificing its performance. By the theory analysis, we design an adjacent address checker which can generate the bank control mask to turn off some power-sensitive circuits of the 2D memory. Experimental results show that the LP2D can reduce the power consumption by 31.7%∼62.9% with less than 1.3% additional hardware cost, as compared with the traditional 2D memory schemes.
An implanted compact antenna for an artificial cardiac pacemaker is proposed. The dimension of the pacemaker system, including the antenna element, is 30mm × 35mm × 7mm. When the antenna is embedded in a semi-solid flat phantom with equivalent electrical properties as the human body, S11 value is -19.2dB at 403.5MHz and the -10dB impedance bandwidth of the antenna is 10MHz (399∼409MHz). The proposed antenna in the phantom has a peak gain of -24.61dBi at 403.5MHz. The measured specific absorption ratio (SAR) value of the proposed antenna is 0.0079W/Kg (1g tissue). Moreover, to estimate the communication performance of the proposed antenna operated in the real environment, a link budget analysis is performed.