IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
Parallelizing the FPGA global routing algorithm on multi-core systems without quality degradation
Arash FarkishAli Jahanian
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JOURNALS FREE ACCESS

2011 Volume 8 Issue 24 Pages 2061-2067

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Abstract

VLSI physical design algorithms are generally nonpolynomial algorithms with very long runtime. In this paper, we parallelize the Pathfinder global routing algorithm -a widely used FPGA routing algorithm- for running on multi-core systems to improve runtime of routing process. Our experimental results show that the runtime of proposed multi-threaded global routing reduces by 47.8% and 70.9% (on average) with 2 and 4 concurrent threads, respectively on a quad-core processor without any quality degradation.

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© 2011 by The Institute of Electronics, Information and Communication Engineers
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