2011 Volume 8 Issue 24 Pages 2106-2111
The power consumption of the 2D memory restricts its usage in vector DSPs for sliding-window applications with irregular memory accesses. This paper introduces a novel Low-Power 2D memory (LP2D), which can effectively reduce the power consumption to the traditional 2D memory without sacrificing its performance. By the theory analysis, we design an adjacent address checker which can generate the bank control mask to turn off some power-sensitive circuits of the 2D memory. Experimental results show that the LP2D can reduce the power consumption by 31.7%∼62.9% with less than 1.3% additional hardware cost, as compared with the traditional 2D memory schemes.