抄録
This paper presents a NMOS-based ESD protection circuit with a low trigger voltage using the 65-nm CMOS process. The proposed ESD protection circuit is achieved by using a gate-substrate triggered technique. We measured the I-V characteristics, temperature characteristics and leakage current under normal operating conditions. The results of the ESD protection circuit were validated using a transmission line pulse (TLP) system. Also, the temperature range from 300K to 500K facilitates the understanding of physical mechanisms for the ESD protection circuit's reliability. From the results, this structure not only exhibited a lower trigger voltage but also has a lower leakage current.
