抄録
A novel two-transistor (2T) programmable element instead of the traditional 6T SRAM element in field programmable gate array (FPGA) is proposed. The key FPGA components, such as lookup table (LUT) and routing structure are modified when applying the 2T element. A restore algorithm is applied to prevent the configuration information lost due to charge leakage. A CAD evaluation demonstrates that the density and the performance of FPGA can be improved by 25% and 19% respectively.
