抄録
In this paper, we design and analyze an asynchronous pipelined FIFO called a micropipeline with the awareness of “place & route” (P&R) on an FPGA device. We use a commercially available 65nm Virtex-5 devices and design a high-speed implementation of the asynchronous four-phase micropipeline with considering its layout on the device. The layout of our design is modified manually to meet timing constraints and to accelerate the speed of circuits. The asynchronous FIFO implemented on the Virtex-5 device shows 452MHz throughput and 648ps per-stage latency at the simulation under the worst case operating condition and around 472MHz throughput is observed at the actual measurement on a real working chip at room temperature.
