抄録
This paper presents a Common-Mode (CM) Built-In Self-Test (BIST) technique for Fully-Differential (FD) Sample-and-Hold (S/H) circuits. Based on the CM test setup, the catastrophic and parametric faults in the MOS switches and hold capacitors can be detected by checking the differential outputs, which should vary around the desired CM output of the FD Operational Amplifier (OpAmp) used in the FD S/H circuits under test. The fault simulation results in circuit-level and the layout design using Rohm 0.18-µm CMOS technology are presented to demonstrate the feasibility of the proposed CM BIST technique for FD S/H circuits.
