A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS

抄録

This paper details the design of a 64×32bit 4-read 2-write register file in TSMC 65nm LP process. The register file avoids cell banking with pseudo-differential sensing scheme. Moreover, this approach enables a fully shareable and completely symmetry cell layout which shows competitive area results. Non-full-swing technique is proposed to avoid over design and improve energy efficiency. As for the timing control module, clocked pull-down circuit cuts off a possible short-current path at high clock frequency. A prototype is implemented in TSMC 65nm LP technology. The measured results demonstrate operation of 0.77GHz, consuming 7.08mW at 1.2V, and occupying 0.018mm².