Bit-error rate improvement of TLC NAND Flash using state re-ordering

抄録

In scaled technologies, large cell-to-cell interference and F-N tunneling disturbance degrade threshold voltage (V_t) window which we can place program states. Moreover, in Triple Layer Cell (TLC) NAND Flash we should place seven program states (P₁ ∼ P₇) in the narrow V_t window, incurring large bit-error rate (BER). In this paper, we propose a state re-ordering technique to increase the efficiency of V_t window utilization in TLC NAND Flash memories. Our simulation results show that under equivalent V_t window sizes, the proposed technique provides 12.5∼18.4% smaller BER compared to conventional Gray-code mapping.