Improved timing closure by analytical buffer and TSV planning in three-dimensional chips

Abstract

In this paper, a mathematical solution for integrated buffer and Through-Silicon Via (TSV) planning in three-dimensional chips is presented in which the optimal location of both buffer and TSV of each net is determined simultaneously. In this method, two-dimensional buffer planning formulation is extended to three-dimensional era. Experimental results show that performance and probability of successful buffer/TSV insertion is increased considerably, especially for large and congested three-dimensional circuits.