IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 9 , Issue 24
Showing 1-14 articles out of 14 articles from the selected issue
  • Donggu Im, Kwyro Lee
    Type: LETTER
    2012 Volume 9 Issue 24 Pages 1813-1822
    Published: December 18, 2012
    Released: December 18, 2012
    JOURNALS FREE ACCESS
    The power handling capability is the most stringent specification for antenna switches, and this is dominated by a significant amount of leakage current of off-state FETs. For achieving maximum power handling capability of antenna switches, new DC I-V (FFI-V) characterization method to characterize RF P1dB point of off-state FETs is proposed and experimental study on optimum DC gate and body bias is performed based on proposed FFI-V method. Using Ron and Coff of minimum channel length MOSFETs at aforementioned optimum DC bias point, antenna switch design methodology for maximum power handling capability and minimum insertion loss is established. The designed SOI CMOS SPDT antenna switch integrated with switch controller shows insertion loss less than 0.5dB and input P1dB greater than +40dBm.
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  • Marco A. Gurrola-Navarro, Agustín S. Medina-Vazquez, Guillermo ...
    Type: LETTER
    2012 Volume 9 Issue 24 Pages 1823-1828
    Published: December 18, 2012
    Released: December 18, 2012
    JOURNALS FREE ACCESS
    We propose two approximations of the inverse wavelet transform implemented with a voltage adder and two analog filters. They work together with a set of scaled band-pass analog filters that perform the wavelet transform of a continuous time signal. With this approach an integrated circuit has been fabricated. On-chip measurements demonstrate signal to reconstruction error ratios up to 25.8dB.
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  • Hamza M. R. Al-Khafaji, S. A. Aljunid, Angela Amphawan, Hilal A. Fadhi ...
    Type: LETTER
    2012 Volume 9 Issue 24 Pages 1829-1834
    Published: December 18, 2012
    Released: December 18, 2012
    JOURNALS FREE ACCESS
    This letter presents a single photodiode detection (SPD) as an effective technique for eradicating both multiple-access interference (MAI) and phase-induced intensity noise (PIIN) in spectral-amplitude coding optical code-division multiple-access (SAC-OCDMA) systems. Mathematical analysis and simulation experiments are used to investigate the spectral efficiency (SE) of SAC-OCDMA systems utilizing different detection techniques. Results show that the SPD technique significantly enhances the SE compared to AND as well as modified-AND subtraction detections.
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  • Tsuyoshi Funaki, Makiko Hirano, Hitoshi Umezawa, Shinichi Shikata
    Type: LETTER
    2012 Volume 9 Issue 24 Pages 1835-1841
    Published: December 18, 2012
    Released: December 18, 2012
    JOURNALS FREE ACCESS
    Diamond is considered to be the most promising wide band gap semiconductor material for the fabrication of power switching devices with respect to the figure of merit. The authors have developed a high voltage and high current diamond Schottky barrier diode (SBD). This paper evaluates the static and dynamic electrical performance of the developed diamond SBD as a power switching device. The experimental results obtained under different operating conditions validate the fast switching, unipolar device characteristics, and high temperature operation capability of the developed diamond SBD.
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  • Yangyang Niu, Wei Li, Ning Li, Junyan Ren
    Type: LETTER
    2012 Volume 9 Issue 24 Pages 1842-1848
    Published: December 18, 2012
    Released: December 18, 2012
    JOURNALS FREE ACCESS
    A novel varactor using single PMOS is proposed. By utilizing the capacitance difference between saturation and linear region, the proposed varactor can improve frequency resolution of a LC-tank based digitally controlled oscillator without introducing extra fixed loading capacitance. A digitally controlled oscillator with the proposed varactor is designed using 0.13µm CMOS technology for verification. Measurement results show that the minimum frequency resolution is achieved around 18.5kHz in a frequency range of 2.4GHz to 3.86GHz, indicating the minimum achievable capacitance step of 30aF. The measured phase noise is -120.6dBc/Hz at 1MHz offset for 3.05GHz carrier. The power consumption is 2.9mW.
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  • Reza Abdollahi, Ali Jahanian
    Type: LETTER
    2012 Volume 9 Issue 24 Pages 1849-1854
    Published: December 21, 2012
    Released: December 21, 2012
    JOURNALS FREE ACCESS
    In this paper, a mathematical solution for integrated buffer and Through-Silicon Via (TSV) planning in three-dimensional chips is presented in which the optimal location of both buffer and TSV of each net is determined simultaneously. In this method, two-dimensional buffer planning formulation is extended to three-dimensional era. Experimental results show that performance and probability of successful buffer/TSV insertion is increased considerably, especially for large and congested three-dimensional circuits.
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  • Y. Zehforoosh, M. Naser-Moghadasi, R. A. Sadeghzadeh, Ch. Ghobadi
    Type: LETTER
    2012 Volume 9 Issue 24 Pages 1855-1860
    Published: December 21, 2012
    Released: December 21, 2012
    JOURNALS FREE ACCESS
    The letter presents the results of a novel miniature fractal monopole antenna that exhibits ultra wideband (UWB) performance. The unique fractal patch generates multiple resonances that results in significant improvement in the antenna's impedance bandwidth of 152%. The antenna essentially radiates omni-directionally and its measured performance exceeds the UWB specifications defined by the Federal Communications Commission (FCC).
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  • Yasar Amin, Rajeev Kumar Kanth, Pasi Liljeberg, Qiang Chen, Li-Rong Zh ...
    Type: LETTER
    2012 Volume 9 Issue 24 Pages 1861-1866
    Published: December 21, 2012
    Released: December 21, 2012
    JOURNALS FREE ACCESS
    In this paper, we demonstrate for the first time an RFID tag antenna manufactured by advanced inkjet printing technology on paper substrate using novel hole-matching technique for reducing the consumption of substrate material and conductive ink while attaining green RFID tags. In-depth electromagnetic analysis is performed methodologically for optimizing the parameters that effectuate the antenna dimensions. The antenna design is optimized for consistent wideband performance and extended read range throughout the complete UHF RFID band (860-960MHz), while exhibiting benchmarking results when n across cardboard cartons filled with metal or water containing objects.
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  • Won-Sup Chung, Myeong-Kyun Kim, Oh Yang
    Type: LETTER
    2012 Volume 9 Issue 24 Pages 1867-1873
    Published: December 26, 2012
    Released: December 26, 2012
    JOURNALS FREE ACCESS
    A simple and high-sensitive resistance-to-time converter is presented for interfacing resistive bridge sensors. It consists of a resistive half bridge, two current-mode Schmitt triggers, a ramp voltage integrator, and two logic gates. HSPICE simulation results with KEC CMOS 0.5µm process exhibit a conversion sensitivity amounting to 5218.3µs/Ω over the resistance deviation range of 0-2Ω, and its linearity error is less than ±0.0005%. The temperature stability of the converter is less than 320ppm/°C in the temperature range of -25-85°C.
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  • Ching-Che Chung, Duo Sheng, Ning-Mi Hsueh
    Type: LETTER
    2012 Volume 9 Issue 24 Pages 1874-1880
    Published: December 28, 2012
    Released: December 28, 2012
    JOURNALS FREE ACCESS
    In this paper, a low-complexity high-performance wear-leveling algorithm which named sequential garbage collection (SGC) for flash memory system design is presented. The proposed SGC outperforms existing designs in terms of wear evenness and low design complexity. The lifetime of the flash memory can be greatly lengthened by the proposed SGC. The proposed SGC doesn’t require any tuning threshold parameter, and thus it can be applied to various systems without prior knowledge of the system environment for threshold tuning. Simulation results show that the maximum block erase count and standard deviation of the block erase count compared to the greedy algorithm are decreased by up to 75% and 94%, respectively.
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  • Nam-Jin Oh, Deuk Heo
    Type: LETTER
    2012 Volume 9 Issue 24 Pages 1881-1886
    Published: December 28, 2012
    Released: December 28, 2012
    JOURNALS FREE ACCESS
    This paper proposes a low-power, low close-in phase-noise voltage-controlled oscillator (VCO) based on Colpitts oscillator. The VCO stacks the Colpitts VCO with a negative conductance cell. By exploiting a bias-level shifting technique, the proposed VCO provides larger output swing, and the close-in phase noise characteristics is improved impressively while consuming very low power. The proposed VCO is designed and simulated in 65nm CMOS technology operating at 2.6GHz with only 0.12mA core current consumption from 0.5V supply voltage. The simulated phase noise of the proposed VCO is -27.6dBc/Hz at 100Hz offset, -54.4dBc/Hz at 1kHz offset, and -117.7dBc/Hz at 1MHz offset frequency, respectively. The calculated figure of merit (FOM) is about -198dBc/Hz at 1MHz offset. Compared to that of the conventional VCO, the phase noise performance is significantly improved by more than 20dB from 100Hz to 1kHz offset, around 15dB at 10kHz offset, and 6dB at 1MHz offset frequency, respectively.
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  • Seongmin Jo, Yong Ho Song
    Type: LETTER
    2012 Volume 9 Issue 24 Pages 1887-1892
    Published: December 28, 2012
    Released: December 28, 2012
    JOURNALS FREE ACCESS
    As semiconductor process technology continues to scale down to the ultra-deep sub-micron level, leakage power becomes a critical design constraint for on-chip networks (OCNs). Power gating is widely used to reduce the OCN leakage power; however, it does not work well with adaptive routing owing to its aggressive use of free links and router buffers to achieve high performance. In this paper, a novel leakage-aware adaptive routing algorithm to increase the power-gating effect by routing packets with minimal link activation is proposed. Experimental results show that the proposed algorithm effectively achieves a reduction in the overall network leakage power of up to 11.6% greater than the conventional adaptive routing algorithm, with a little sacrificing network bandwidth.
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  • Kaita Imai, Keita Yasutomi, Keiichiro Kagawa, Shoji Kawahito
    Type: LETTER
    2012 Volume 9 Issue 24 Pages 1893-1899
    Published: December 28, 2012
    Released: December 28, 2012
    JOURNALS FREE ACCESS
    This paper proposes a distributed ramp signal generator of column-parallel single-slope ADCs for CMOS image sensors. This architecture does not require any power-hungry amplifiers of the conventional one but consists of miniaturized column-wise ramp signal generators connected together by metal wires, which achieves high linearity and high uniformity. Simulation results show less than 1LSB nonlinear error of the ramp signal at 12-bit ADC resolution is attained only by having the consumption current of 6.4mA and the area of 2.4mm2 which are much smaller than the conventional one. It is also confirmed that 100mΩ resistive connection attains less than 1LSB gain error mismatching, even though the mismatch of the column-wise ramp signal generators is as large as 20%.
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  • Kamran Delfan Hemmati, Mojtaba Behzad Fallahpour, Abbas Golmakani, Kam ...
    Type: LETTER
    2012 Volume 9 Issue 24 Pages 1900-1905
    Published: December 28, 2012
    Released: December 28, 2012
    JOURNALS FREE ACCESS
    In this paper a new high speed hybrid Full Adder with low power consumption is presented. Furthermore, after determining topology a proposed CAD (Computer Aided Design) with a proposed multi objective genetic algorithm will be used to optimize the high speed hybrid Full Adder. The size of generative Full Adder transistors is introduced to algorithm as the inputs and the average power consumption and max delay are introduced as the outputs. After performing the algorithm, several results will be obtained as they have no priority to each other, so designer can select whichever according to his need. Simulation results show that, proposed structure uses less average power. Algorithm program is written in MATLAB and the circuit simulated by Hspice with 0.18μ technology.
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