A high-speed hybrid Full Adder with low power consumption

Abstract

In this paper a new high speed hybrid Full Adder with low power consumption is presented. Furthermore, after determining topology a proposed CAD (Computer Aided Design) with a proposed multi objective genetic algorithm will be used to optimize the high speed hybrid Full Adder. The size of generative Full Adder transistors is introduced to algorithm as the inputs and the average power consumption and max delay are introduced as the outputs. After performing the algorithm, several results will be obtained as they have no priority to each other, so designer can select whichever according to his need. Simulation results show that, proposed structure uses less average power. Algorithm program is written in MATLAB and the circuit simulated by Hspice with 0.18μ technology.