Low-energy block-level instantaneous comparison 7T SRAM for dual modular redundancy

Shunsuke Okumura; Yohei Nakata; Koji Yanagida; Yuki Kagiyama; Shusuke Yoshimoto; Hiroshi Kawaguchi; Masahiko Yoshimoto

doi:10.1587/elex.9.470

LETTER

Low-energy block-level instantaneous comparison 7T SRAM for dual modular redundancy

Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto

著者情報

キーワード: SRAM, 7T bitcell, comparison circuit, DMR

ジャーナルフリー

2012 年 9 巻 6 号 p. 470-476

DOI https://doi.org/10.1587/elex.9.470

詳細

抄録

This paper proposes a 7T SRAM that realizes a block-level instantaneous comparison feature. The proposed SRAM is useful for operation results comparison in dual modular redundancy (DMR). The data size that can be instantaneously compared is scalable using the proposed structure. The 1-Mb SRAM comprises 16-Kb blocks in which 8-Kb data can be compared in 130.0ns. The proposed scheme reduces energy consumption in data comparison to 1/418, compared to that of a parallel cyclic redundancy check (CRC) circuit.

責任著者(Corresponding author)

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