Design a 10-Bit 100MHz pipelined ADC using RB-OTA in 90nm CMOS technology

抄録

In this paper a low consumption 10bits pipelined analogue to digital converter (ADC) by using a new operational transconductance amplifier (OTA) is introduced. The ADC is designed to work at 100MHz with 1 volt bias voltage in a CMOS 90nm technology. The simulation results at frequency of 5MHz show the spurious free dynamic range and signal to noise ratio of 66dB and 58.4dB (9.4 ENOB) respectively. The power consumption for the designed ADC including digital and analogue parts is 14.4mW.