IEICE Electronics Express
A pipelined VLSI architecture for Sample Adaptive Offset (SAO) filter and deblocking filter of HEVC
Sha ShenWeiwei ShenYibo FanXiaoyang Zeng
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JOURNALS FREE ACCESS Advance online publication

Article ID: 10.20130272

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Abstract

This paper present a high throughput design for Sample Adaptive offset (SAO) filter and deblocking filter used in an HEVC decoder. A five-stage pipelined architecture is proposed to support both SAO filter and deblocking filter on a 32x32 pixel block basis. Deblocking filter and SAO filter can work simultaneously in consecutive pipeline stages. The on-chip SRAM can also be shared by deblocking filter and SAO filter. Coupled with the novel filter order, an interlaced SRAM memory mapping scheme is proposed to increase the throughput for deblocking filter. The experimental results show that our design can support 4Kx2K@60fps (4096x2304) HEVC video sequence at the working frequency of only 60.8MHz.

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© 2013 by The Institute of Electronics, Information and Communication Engineers

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