抄録
High performance bootstrapped switch is critical to high speed analog-to-digital converters (ADCs). This paper presents a novel CMOS bootstrapped switch which achieves rail-to-rail input range with greatly reduced bootstrap capacitance while maintaining high speed based on the precharge technique and charge leakage control. The proposed scheme is implemented in a 65 nm CMOS technology. Simulation results demonstrate that the proposed bootstrapped switch can achieve full-swing input range at 200 MHz Nyquist with a chip area of 25 μm by 20 μm.
