抄録
Recently, use of high-throughput data with high-dimensional feature space such as images and microarrays have increased significantly. Therefore, a fast and efficient method to process these data is required. In this paper, we propose a novel semi-naive Bayes classification method based on stochastic discrimination theory and implement it in hardware. The hardware implemented on a FPGA with massively parallel computation enables fast and efficient processing, because the algorithm of the proposed method is very suitable for parallel computation. The implemented hardware takes 0.378 µs at 106 MHz clock to process given one test data. In addition, we evaluate the performance of the proposed method through experiments on various datasets. In the experimental results, our proposed method shows competitive performance compared with conventional machine learning methods.
