Abstract
A successive approximation time-to-digital converter (TDC) is presented. The proposed TDC is based on the vernier charging method, and characterized with its timing resolution independent of the period of the reference clock. Further by including voltage ratio together with both current and capacitor ratios to enlarge the pulse stretch factor, a higher timing resolution is attained. The circuit is implemented in a 130 nm CMOS process and occupies an area of 0.32×0.21 mm2. According to the simulation results, the proposed TDC achieves typically 6.25 ps resolution and consumes 0.9 mW from a 1.5 V supply voltage.
