抄録
In this article a novel charge pump circuit is introduced. The proposed circuit utilizes a bulk driven cascode current mirror through an adaptive gate bias technique, that results in a high output impedance over a very wide output voltage range, accurate Charge/Discharge current matching, which minimizes the steady-state phase error in a phase-locked loop (PLL), and low transient glitches. The current variation is less than 0.5µA or 1% over output range. Therefore proposed circuit stabilizes the loop bandwidth of the charge pump PLL and maximizes the dynamic range. The charge pump is designed and simulated under the power supply of 1.8 V in 0.18µm CMOS technology to verify the efficiency of the proposed techniques. Monte Carlo process variations and mismatch simulations show that the current variation in the proposed charge pump is very low.
