抄録
Energy harvesting is a technique that captures an effective power source. However, the energy obtained from power resources in the environment is insufficient, as only low levels of voltage/current can be generated from it. Therefore, the power consumption of logic circuits for energy harvesting has to be reduced. To achieve low power consumption, we may consider two low-power techniques: the adiabatic logic circuit and the sub-threshold CMOS logic circuit. In this paper, we propose a new CMOS logic circuit that combines the adiabatic logic circuit with the sub-threshold logic circuit. The proposed circuit employs two-phase clock supply voltages that have different amplitude and frequency. We design and implement NAND, XOR, half-adder, full-adder, and 4×4-bit multiplier circuits using the proposed method. The simulation and the measurement results show that the proposed circuit has an ultra-low-power characteristic compared with the conventional circuit.
