IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543

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A Low-Cost FPGA Implementation of Multi-Channel FIR Filter with Variable Bandwidth
Sang Yoon Park
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ジャーナル フリー 早期公開

論文ID: 12.20150702

この記事には本公開記事があります。
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This paper proposes a low-cost implementation of a multi-channel FIR filter on FPGA, where each channel can have variable bandwidth and coefficients. New structures of the tapped-delay line and the coefficient bank unit based on time-division multiplexing are proposed. Pipelined adder tree is used to expedite the filtering process without disturbing generation of control signals for multi-channel data access. From implementation results, it is found that the proposed 39-tap FIR filter involves 32% less number of slice registers as well as 65% less number of DSP blocks than the Xilinx FIR Core 5.0, and also supports variable bandwidth.
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