抄録
This paper proposes a low-cost implementation of a multi-channel FIR filter on FPGA, where each channel can have variable bandwidth and coefficients. New structures of the tapped-delay line and the coefficient bank unit based on time-division multiplexing are proposed. Pipelined adder tree is used to expedite the filtering process without disturbing generation of control signals for multi-channel data access. From implementation results, it is found that the proposed 39-tap FIR filter involves 32% less number of slice registers as well as 65% less number of DSP blocks than the Xilinx FIR Core 5.0, and also supports variable bandwidth.
