Variation-resilient pipelined timing tracking circuit for SRAM sense amplifier

Zhengping Li; Chunyu Peng; Wenjuan Lu; Lijun Guan; Youwu Tao; Xincun Ji; Junning Chen

doi:10.1587/elex.13.20150951

This article has now been updated. Please use the final version.

Variation-resilient pipelined timing tracking circuit for SRAM sense amplifier

Zhengping Li, Chunyu Peng, Wenjuan Lu, Lijun Guan, Youwu Tao, Xincun Ji, Junning Chen

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Keywords: variation-resilient, timing tracking, pipelined replica bitline, sense amplifier enable, SRAM

JOURNAL FREE ACCESS Advance online publication

Article ID: 13.20150951

DOI https://doi.org/10.1587/elex.13.20150951

The final version of this article is now available: Vol. 13 (2016), No. 7 pp. 20150951-20150951

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Abstract

A resilient tracking circuit for suppressing the timing variation of SRAM sense amplifier enable (SAE) signal is proposed. Pipelined replica bitline technique is used to favour the desired design. Simulation results show that the cycle time is reduced by ∼27% owing to ∼70% reduction of the standard deviation of SAE at a 1.05V supply voltage in 28nm CMOS technology with four-stage pipeline.

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