Comparison of Single-Event Transients of T-gate Core and IO device in 130 nm Partially Depleted Silicon-on-Insulator Technology

抄録

Many papers have confirmed that the single event vulnerability of semiconductor devices significantly increase with power supply voltage drop, rendering considerable challenges for the radiation harden design as per the development of Moore's law. The higher the supply voltage of the chip scaling down, the greater severity of these problems. In this article, SET pulse widths induced by heavy ion of T-gate 1.2V Core and 3.3V IO devices fabricated by a 130nm partially depleted silicon-on-insulator technology were directly measured. We discovered that, by adjusting the design parameters and choosing an appropriate device W/L ratio, different power supply voltage SOI devices are able to achieve the same sensitivity for the single event, irrespective of supply voltage. The distribution of SET-pulse widths ranges from 210 to 735 ps under a constant LET of 37.6 MeV-cm²/mg, and the single event transient vulnerability of T-gate 1.2V Core and 3.3V IO devices is similar, which is instructive for the low-voltage and low-power circuit application.