抄録
On the basis of the systematic study of stitching techniques, a large area, 28.3mm × 38.8mm, 42 Mega pixels CMOS Imaging Sensor (CIS) had been demonstrated on 12 inch silicon wafer in a 0.055μm CMOS process. By scanning a reticle across a wafer of silicon, smaller arrays can be stitched together to construct larger area sensors. Meanwhile, in order to verify the feasibility and capability of stitching, a 203mm × 179mm, 1.8 Billion pixels CIS was also created without any performance deficiency.
