A nanosecond-accuracy clock synchronization circuit for IEEE 1588-2008 using tapped delay lines

抄録

This letter presents a high-accuracy clock synchronization circuit, which reduces the time error between the master and slave clocks to less than 1 ns. To suppress quantization errors resulted in generation of timestamps and pulse-per-second (PPS) signals, time-to-digital converters (TDC) and digital-to-time converters (DTC) have been implemented using tapped delay lines. The proposed scheme provides a cost-effective solution for applications of clock synchronization since it works on gigabit Ethernet using copper media (1000BASE-T) without any extra clock synthesis. Experimental results show that the two nodes over network share synchronized timing within the error between -0.74 ns and 0.89 ns.