Enhanced 3×VDD-tolerant ESD clamp circuit with stacked configuration

Xiaoyun Li; Houpeng Chen; Qian Wang; Xi Li; Yu Lei; Qi Zhang; Xi Fan; Jiajun Hu; Zhen Tian; Zhitang Song

doi:10.1587/elex.14.20160901

This article has now been updated. Please use the final version.

Enhanced 3×VDD-tolerant ESD clamp circuit with stacked configuration

Xiaoyun Li, Houpeng Chen, Qian Wang, Xi Li, Yu Lei, Qi Zhang, Xi Fan, Jiajun Hu, Zhen Tian, Zhitang Song

Author information

Xiaoyun Li
State Key Laboratory of Functional Materials for Informatics (Shanghai Institute of Microsystem and Information Technology), Chinese Academy of Sciences
Houpeng Chen
State Key Laboratory of Functional Materials for Informatics (Shanghai Institute of Microsystem and Information Technology), Chinese Academy of Sciences
Qian Wang
State Key Laboratory of Functional Materials for Informatics (Shanghai Institute of Microsystem and Information Technology), Chinese Academy of Sciences
Xi Li
State Key Laboratory of Functional Materials for Informatics (Shanghai Institute of Microsystem and Information Technology), Chinese Academy of Sciences
Yu Lei
State Key Laboratory of Functional Materials for Informatics (Shanghai Institute of Microsystem and Information Technology), Chinese Academy of Sciences
Qi Zhang
State Key Laboratory of Functional Materials for Informatics (Shanghai Institute of Microsystem and Information Technology), Chinese Academy of Sciences
Xi Fan
State Key Laboratory of Functional Materials for Informatics (Shanghai Institute of Microsystem and Information Technology), Chinese Academy of Sciences
Jiajun Hu
State Key Laboratory of Functional Materials for Informatics (Shanghai Institute of Microsystem and Information Technology), Chinese Academy of Sciences
Zhen Tian
State Key Laboratory of Functional Materials for Informatics (Shanghai Institute of Microsystem and Information Technology), Chinese Academy of Sciences
Zhitang Song
State Key Laboratory of Functional Materials for Informatics (Shanghai Institute of Microsystem and Information Technology), Chinese Academy of Sciences

Keywords: Electrostatic discharge (ESD), power clamp, mixed-voltage I/O, high discharge current, SOI CMOS process, 28nm high-k CMOS process

JOURNAL FREE ACCESS Advance online publication

Article ID: 14.20160901

DOI https://doi.org/10.1587/elex.14.20160901

The final version of this article is now available: Vol. 14 (2017), No. 2 pp. 20160901-20160901

Details

Abstract

A new stacked ESD protection circuit which could receive 3×VDD input signals by using only 1×VDD low-voltage devices for mixed-voltage I/O buffer was presented. Four transistors were added in this design to transfer bias voltages or ESD voltages. This circuit was simulated in 0.18µm silicon-on-insulator (SOI) CMOS process and 28nm HKMG CMOS technology. Spectre-simulation results showed that the ESD discharge current is increased by 2 times and the discharge current is decreased to nA magnitudes compared to the conventional circuit.

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